Simultaneous switching noise (SSN) in an integrated circuit (IC) and the IC package may be attributed to two primary factors: the mutual inductive coupling among switching input/output (I/O) buffers and the impedance profile of a power distribution network (PDN). In essence, reducing SSN is a design-cost issue. While designers can minimize the mutual inductive coupling by increasing the ratio of ground pins (or return-current pins) to I/O buffers, this approach sacrifices I/O buffer densities. Engineers can improve PDN performance by increasing on-die capacitance and adding on-package decoupling capacitors, but this approach increases costs.
Furthermore, due to the programmable nature of programmable logic devices (PLD), they fit into a wide variety of user applications, and it is useful for designers to have a tool to determine their own SSN budget without additional costs. Ideally, this kind of tool requires instantaneous and accurate result predictions for various I/O buffer assignments and ideally would provide an optimum buffer assignment under certain design constraints. In the past, designers have constructed system-level, “SPICE-like” models to anticipate SSN in PLD systems. These models are based on an understanding of SSN cause mechanisms and correlate well with bench measurements, helping IC and packaging designers improve designs.
However, these models are so complicated that they require signal/power integrity expertise to perform time-consuming, system-level simulations. It is cumbersome for all designers to perform the same level SSN analysis without considering their different design margins. Therefore, there is a need for a tool to help users execute a comprehensive SSN analysis in a short design cycle, though the invention claimed below has applicability to other applications beyond this particular application, as will become apparent from the following description and the drawings.
It is within this context that the invention arises.